Scheduling feasibility, Processor processor1 : 1) Feasibility test based on the processor utilization factor : - The feasibility interval is 21494334923807697900000.0, see Leung and Merill (1980) from [21]. - 1.60348315987809803E+22 units of time are unused in the feasibility interval. - Number of cores hosted by this processor : 1. - Processor utilization factor with deadline is 0.25400 (see [1], page 6). - Processor utilization factor with period is 0.25400 (see [1], page 6). - In the preemptive case, with RM, the task set is schedulable because the processor utilization factor 0.25400 is equal or less than 0.69919 (see [1], page 16, theorem 8). 2) Feasibility test based on worst case response time for periodic tasks : - Worst case task response time : (see [2], page 3, equation 4). T5 => 1 T10 => 2 T15 => 3 T20 => 4 T25 => 5 T30 => 6 T35 => 7 T40 => 8 T45 => 9 T50 => 10 T55 => 11 T60 => 12 T65 => 13 T70 => 14 T75 => 15 T80 => 16 T85 => 17 T90 => 19 T95 => 20 T100 => 21 T105 => 22 T110 => 23 T115 => 24 T120 => 25 T125 => 26 T130 => 27 T135 => 28 T140 => 29 T145 => 30 T150 => 31 T155 => 32 T160 => 33 T165 => 34 T170 => 37 T175 => 38 T180 => 39 T185 => 40 T190 => 41 T195 => 42 T200 => 43 - All task deadlines will be met : the task set is schedulable. Scheduling feasibility, Processor processor2 : 1) Feasibility test based on the processor utilization factor : - The feasibility interval is 21800265212911042800000.0, see Leung and Merill (1980) from [21]. - 1.12324984003146936E+22 units of time are unused in the feasibility interval. - Number of cores hosted by this processor : 1. - Processor utilization factor with deadline is 0.48475 (see [1], page 6). - Processor utilization factor with period is 0.48475 (see [1], page 6). - In the preemptive case, with RM, the task set is schedulable because the processor utilization factor 0.48475 is equal or less than 0.69919 (see [1], page 16, theorem 8). 2) Feasibility test based on worst case response time for periodic tasks : - Worst case task response time : (see [2], page 3, equation 4). T1 => 1 T6 => 2 T11 => 3 T16 => 4 T21 => 6 T26 => 7 T31 => 8 T36 => 10 T41 => 11 T46 => 12 T51 => 14 T56 => 15 T61 => 16 T66 => 18 T71 => 19 T76 => 20 T81 => 23 T86 => 24 T91 => 26 T96 => 27 T101 => 28 T106 => 30 T111 => 31 T116 => 32 T121 => 34 T126 => 35 T131 => 36 T136 => 39 T141 => 40 T146 => 42 T151 => 44 T156 => 46 T161 => 47 T166 => 48 T171 => 50 T176 => 51 T181 => 52 T186 => 54 T191 => 56 T196 => 58 - All task deadlines will be met : the task set is schedulable. Scheduling feasibility, Processor processor3 : 1) Feasibility test based on the processor utilization factor : - The feasibility interval is 1883777015333905050000000.0, see Leung and Merill (1980) from [21]. - 1.19571979891968761E+24 units of time are unused in the feasibility interval. - Number of cores hosted by this processor : 1. - Processor utilization factor with deadline is 0.36525 (see [1], page 6). - Processor utilization factor with period is 0.36525 (see [1], page 6). - In the preemptive case, with RM, the task set is schedulable because the processor utilization factor 0.36525 is equal or less than 0.69919 (see [1], page 16, theorem 8). 2) Feasibility test based on worst case response time for periodic tasks : - Worst case task response time : (see [2], page 3, equation 4). T2 => 1 T7 => 2 T12 => 3 T17 => 4 T22 => 5 T27 => 6 T32 => 7 T37 => 9 T42 => 10 T47 => 11 T52 => 12 T57 => 13 T62 => 14 T67 => 16 T72 => 17 T77 => 18 T82 => 19 T87 => 20 T92 => 21 T97 => 23 T102 => 24 T107 => 26 T112 => 27 T117 => 28 T122 => 30 T127 => 31 T132 => 32 T137 => 33 T142 => 34 T147 => 35 T152 => 37 T157 => 38 T162 => 39 T167 => 40 T172 => 41 T177 => 44 T182 => 45 T187 => 46 T192 => 47 T197 => 48 - All task deadlines will be met : the task set is schedulable. Scheduling feasibility, Processor processor4 : 1) Feasibility test based on the processor utilization factor : - The feasibility interval is 506995035287016988000000000.0, see Leung and Merill (1980) from [21]. - 3.53239427004042288E+26 units of time are unused in the feasibility interval. - Number of cores hosted by this processor : 1. - Processor utilization factor with deadline is 0.30327 (see [1], page 6). - Processor utilization factor with period is 0.30327 (see [1], page 6). - In the preemptive case, with RM, the task set is schedulable because the processor utilization factor 0.30327 is equal or less than 0.69919 (see [1], page 16, theorem 8). 2) Feasibility test based on worst case response time for periodic tasks : - Worst case task response time : (see [2], page 3, equation 4). T3 => 1 T8 => 2 T13 => 3 T18 => 4 T23 => 5 T28 => 6 T33 => 7 T38 => 8 T43 => 9 T48 => 10 T53 => 11 T58 => 13 T63 => 14 T68 => 15 T73 => 16 T78 => 17 T83 => 18 T88 => 19 T93 => 20 T98 => 21 T103 => 22 T108 => 24 T113 => 25 T118 => 26 T123 => 27 T128 => 29 T133 => 30 T138 => 31 T143 => 32 T148 => 33 T153 => 35 T158 => 36 T163 => 37 T168 => 38 T173 => 39 T178 => 40 T183 => 41 T188 => 42 T193 => 43 T198 => 44 - All task deadlines will be met : the task set is schedulable. Scheduling feasibility, Processor processor5 : 1) Feasibility test based on the processor utilization factor : - The feasibility interval is 13977506116350182600000.0, see Leung and Merill (1980) from [21]. - 1.01448337118741240E+22 units of time are unused in the feasibility interval. - Number of cores hosted by this processor : 1. - Processor utilization factor with deadline is 0.27420 (see [1], page 6). - Processor utilization factor with period is 0.27420 (see [1], page 6). - In the preemptive case, with RM, the task set is schedulable because the processor utilization factor 0.27420 is equal or less than 0.69919 (see [1], page 16, theorem 8). 2) Feasibility test based on worst case response time for periodic tasks : - Worst case task response time : (see [2], page 3, equation 4). T4 => 1 T9 => 2 T14 => 3 T19 => 4 T24 => 5 T29 => 6 T34 => 7 T39 => 8 T44 => 9 T49 => 10 T54 => 11 T59 => 12 T64 => 13 T69 => 14 T74 => 16 T79 => 17 T84 => 18 T89 => 19 T94 => 20 T99 => 21 T104 => 22 T109 => 23 T114 => 24 T119 => 25 T124 => 26 T129 => 27 T134 => 28 T139 => 30 T144 => 31 T149 => 33 T154 => 34 T159 => 35 T164 => 36 T169 => 37 T174 => 38 T179 => 39 T184 => 40 T189 => 41 T194 => 42 T199 => 44 - All task deadlines will be met : the task set is schedulable.