package Shared_Memory_bank_Example

public 
	with Cheddar_Multicore_Properties;
	with aadlv3;
	with Cheddar_Transformation_Properties;
	with multicore_crossbar_units;
	with memory_units;
	
	
	------------------------------------------------
	 	
 	  
  thread function
  properties
    Dispatch_Protocol => Periodic;
    Period => 250 ms;
    Deadline => 250 ms;
    Compute_Execution_Time => 25 ms .. 25 ms;
    Priority => 8 ;
  end function;
  thread implementation function.Impl
  end function.Impl;
  
  process Software
  end Software;

  process implementation Software.Impl
  subcomponents
    T1 : thread function.Impl {Period => 125 ms; Deadline => 125 ms; Compute_Execution_Time => 25 ms .. 25 ms;};
    T2 : thread function.Impl {Period => 25 ms; Deadline => 25 ms; Compute_Execution_Time => 5 ms .. 5 ms;};
    T3 : thread function.Impl {Compute_Execution_Time => 50 ms .. 50 ms;};
  end Software.Impl;
  
	------------------------------------------------
	
	memory Memory_Bank
	end Memory_Bank;

	memory implementation Memory_Bank.impl
		properties
			Cheddar_Multicore_Properties::Private_Access_Latency => 1 ms .. 10 ms;	
			Cheddar_Multicore_Properties::Shared_Access_Latency => 1 us .. 20 us;	
	end Memory_Bank.impl;

	------------------------------------------------
	system processor_with_memory_latency
	end processor_with_memory_latency;
	
	system implementation processor_with_memory_latency.global
	subcomponents
		cores : system  multicore_crossbar_units::dual_core.impl;
		bank1 : system memory_units::DRAM_chip.impl 
			{Cheddar_Multicore_Properties::Private_Access_Latency => 2 us .. 10 us;};
		bank2 : system memory_units::DRAM_chip.impl 
			{Cheddar_Multicore_Properties::Private_Access_Latency => 3 us .. 20 us;};
		soft  : process Software.impl;
	properties
	    actual_processor_binding => (reference(cores)) applies to soft;
	    actual_memory_binding => (reference(cores)) applies to bank1;
	    actual_memory_binding => (reference(cores)) applies to bank2;
	    aadlv3::System_Soc_Type => SoC_Processing_Unit;
	end processor_with_memory_latency.global;
		
		
		
	system implementation processor_with_memory_latency.partitionned
	subcomponents
		cores : system  multicore_crossbar_units::dual_core.impl;
		bank1 : system  memory_units::DRAM_chip.impl 
			{Cheddar_Multicore_Properties::Private_Access_Latency => 2 us .. 10 us;};
		bank2 : system memory_units::DRAM_chip.impl 
			{Cheddar_Multicore_Properties::Private_Access_Latency => 3 us .. 20 us;};
		soft  : process Software.impl;
	properties
	    aadlv3::System_Soc_Type => SoC_Processing_Unit;
	    actual_processor_binding => (reference(cores.core1)) applies to soft.T1;
	    actual_processor_binding => (reference(cores.core2)) applies to soft.T2;
	    actual_memory_binding => (reference(cores.core1)) applies to bank1;
	    actual_memory_binding => (reference(cores.core2)) applies to bank2;
	end processor_with_memory_latency.partitionned;
	
	
end Shared_Memory_bank_Example;