package DRAM_Arbiter_Memory_bank_Example

public 
	with Cheddar_Multicore_Properties;
	with aadlv3;
	with Cheddar_Transformation_Properties;
	with multicore_crossbar_units;
	
	
	---------------------------------------------------
 	--   Hardware model components
 	--------------------------------------------------
 	
	
	memory Memory_Bank
	end Memory_Bank;

	memory implementation Memory_Bank.impl
	properties
    	Cheddar_Multicore_Properties::Data_Bus_Turn_Around_And_Rank_To_Bank_Switch_Delay => 10 us .. 20 us; 
    	Cheddar_Multicore_Properties::Inter_Bank_Row_Activate_Timing_Constraints => 11 us .. 21 us; 
    	Cheddar_Multicore_Properties::Command_Bus_Scheduling_Time => 12 us .. 22 us; 
    	Cheddar_Multicore_Properties::Maximum_Number_of_Row_Hits => 13 us .. 23 us; 
    	Cheddar_Multicore_Properties::Consecutive_Row_Hit_Requests => 14 us .. 24 us; 
    	Cheddar_Multicore_Properties::Row_Conflict_Service_Time => 15 us .. 25 us; 
	end Memory_Bank.impl;


	system cores_with_memory_bank
	end cores_with_memory_bank;
	
	system implementation cores_with_memory_bank.impl
	subcomponents
		core1       : processor multicore_crossbar_units::uni_core;
		core2       : processor multicore_crossbar_units::uni_core;
		core3_and_4 : system multicore_crossbar_units::dual_core;
		bank1 : memory Memory_Bank.impl;
		bank2 : memory Memory_Bank.impl;
    properties
  		aadlv3::System_Soc_Type => SoC_Processing_Unit;
  		Cheddar_Transformation_Properties::Exported_Attribute_Time_Units => MicroSecond;
	end cores_with_memory_bank.impl;
	
	---------------------------------------------------
 	--   Root system definition and software components
 	---------------------------------------------------
 	
 	  
  thread function
  properties
    Dispatch_Protocol => Periodic;
    Period => 250 ms;
    Deadline => 250 ms;
    Compute_Execution_Time => 25 ms .. 25 ms;
    Priority => 8 ;
  end function;
  thread implementation function.Impl
  end function.Impl;
  
  process Software
  end Software;

  process implementation Software.Impl
  subcomponents
    T1 : thread function.Impl {Period => 125 ms; Deadline => 125 ms; Compute_Execution_Time => 25 ms .. 25 ms;};
    T2 : thread function.Impl {Period => 25 ms; Deadline => 25 ms; Compute_Execution_Time => 5 ms .. 5 ms;};
    T3 : thread function.Impl {Compute_Execution_Time => 50 ms .. 50 ms;};
  end Software.Impl;
  
  	
  system DRAM_memory_bank_arbiter_root_system
  end DRAM_memory_bank_arbiter_root_system;
	
  System implementation DRAM_memory_bank_arbiter_root_system.impl
		subcomponents
		   cpu : system cores_with_memory_bank;
		   soft : process Software.impl;
  	properties
  			actual_processor_binding => (reference(cpu)) applies to soft;
			Scheduling_Protocol => (RMS) applies to cpu;
  end DRAM_memory_bank_arbiter_root_system.impl;
  
  	
	
end DRAM_Arbiter_Memory_bank_Example;