package memory_units
public
    with aadlv3;
    with multicore_bus_units;
    with Cheddar_Multicore_Properties;
    
	memory Cache
	end Cache;

	memory implementation Cache.impl
		properties
	       Memory_Size => 1024Bytes;
	       Cheddar_Multicore_Properties::Line_Size => 16Bytes;
	       Cheddar_Multicore_Properties::Cache_Type => Instruction_Cache;  	    
	       Cheddar_Multicore_Properties::Cache_Level => 1;
	       Cheddar_Multicore_Properties::Associativity => 1;
	       Cheddar_Multicore_Properties::Cache_Size => 1024;
	       Cheddar_Multicore_Properties::Block_Reload_Time => 1 us .. 2 us;
	end Cache.impl;

	
	memory Bank_Memory
	end Bank_Memory;

	memory implementation Bank_Memory.impl
	end Bank_Memory.impl;
		
		
		
	---------------------------------------------------
 	--   Hardware model components for a DRAM chip
 	--------------------------------------------------
 	
 	
system DRAM_chip
end DRAM_chip;
  
system implementation DRAM_chip.impl
 	subcomponents
  		banks : memory memory_units::Bank_Memory [7];
  		controller : system DRAM_controller.impl;
  	properties
  		aadlv3::System_Soc_Type => Soc_Memory_Unit;
end DRAM_chip.impl;
  	
 system  DRAM_controller
 end DRAM_controller;
  
 system implementation DRAM_controller.impl
 	subcomponents
  		memory_requests : process DRAM_request_demand.impl;
  		DRAM_controller_scheduler : processor multicore_bus_units::uni_core;
  	properties
  		aadlv3::System_Soc_Type => Soc_Processing_Unit;
  		Actual_Processor_Binding => (reference (DRAM_controller_scheduler)) applies to memory_requests;
 end DRAM_controller.impl;

 process  DRAM_request_demand
 end DRAM_request_demand;
   	
 process implementation DRAM_request_demand.impl
  	subcomponents
  		memory_requests : thread Memory_Request.impl [10];
 end DRAM_request_demand.impl;
 
 thread Memory_Request
 end Memory_Request;
 
 thread implementation Memory_Request.impl
 	properties
 		Dispatch_Protocol => Periodic;
 		Period => 10 us;
 end Memory_Request.impl;
 
 
end memory_units;