archi_model_spec("ValidationExample2",L) :-
L = [ sw_archi(log_upg),
tasks([t0, t1, t2, t3]),
processing_elements([c0, c1]),
resources([ic0,ic1]),
a_type(c0,processing),       
a_type(c1,processing),
a_type(ic0,memory),       
a_type(ic1,memory),
am_PE_use(c0,[ic0]),
am_PE_use(c1,[ic1]),  
ha_independent(c0),
ha_independent(c1),
dm_PE_actual(t0,c0),
dm_PE_actual(t1,c0),
dm_PE_actual(t2,c1),
dm_PE_actual(t3,c1),
dm_PE_allowed(t0,[c0]), 
dm_PE_allowed(t1,[c0]),
dm_PE_allowed(t2,[c1]),
dm_PE_allowed(t3,[c1]),
dm_PE_scheduling(c0,t0, sched(posix_1003_highest_priority_first_protocol,preemptive)),
dm_PE_scheduling(c0,t1, sched(posix_1003_highest_priority_first_protocol,preemptive)),
dm_PE_scheduling(c1,t2, sched(posix_1003_highest_priority_first_protocol,preemptive)),
dm_PE_scheduling(c1,t3, sched(posix_1003_highest_priority_first_protocol,preemptive)),
a_type(mb0,interconnect),
a_conn_type(mb0,bus),
am_time(c1,mb0,interval( 500, 500, 1000)),
am_time(c0,mb0,interval( 0, 500, 1000)),
a_proc_type(c1,processor),
a_proc_type(c0,processor),
a_proc_isa(c0,sparc_V8),
a_proc_isa(c1,sparc_V8),
a_proc_speed(c0, 100000000),
a_proc_speed(c1, 100000000),
a_mem_type(ic0,instruction_cache_type),
a_mem_type(ic1,instruction_cache_type),
a_mem_cache_associativity(ic0, 1),
a_mem_cache_associativity(ic1, 1),
a_mem_cache_level(ic1,1),
a_mem_cache_level(ic0,1),
a_mem_cache_size(ic0, 1024),
a_mem_cache_size(ic1, 1024),
a_mem_cache_line_size(ic0, 16),
a_mem_cache_line_size(ic1, 16),
a_mem_cache_miss_time(ic0, 1000),
a_mem_cache_miss_time(ic1, 1000),
end_with_success ].