System to model and assumptions

Typical solution


    ---------------------------------------------------    
    -- Property for Memory  units modeling 
    ---------------------------------------------------   
 
   
    -- Memory and/or memory bus latency properties
    --

    Private_Access_Latency : Time_Range applies to (memory, system);    
    Shared_Access_Latency : Time_Range applies to (memory, system);        
  
      
    ---------------------------------------------------    
    -- Memory bank properties
    ---------------------------------------------------    

    
    -- Properties for shared memory DRAM banks analysis of 
    -- Kim, de Nizz and Andersson
    --
    Data_Bus_Turn_Around_And_Rank_To_Bank_Switch_Delay : Time_Range applies to (memory, system); 
    Inter_Bank_Row_Activate_Timing_Constraints : Time_Range applies to (memory, system); 
    Command_Bus_Scheduling_Time : Time_Range applies to (memory, system); 
    Maximum_Number_of_Row_Hits : Time_Range applies to (memory, system); 
    Consecutive_Row_Hit_Requests : Time_Range applies to (memory, system); 
    Row_Conflict_Service_Time : Time_Range applies to (memory, system);